x86 model memory latency, L1/L2 cache, and its effects on suitability for hardware as routing/switching device

/u/gonzopacho I was reading this thread https://www.reddit.com/r/networking/comments/6upchy/can_a_bsd_system_replicate_the_performance_of/

and I was wondering if you could speak to the current state of x86 hardware, if there's any specific models that look promising for advances in reduction of memory latency, increases in l1/l2 caching, other criteria that benefit the hardware for use as a routing/switching device (?)

Also, you specifically mention Ryzen memory latency as being slower than Intel (98 ns vs 70 ns I believe) - do you know if this also applies to Epyc chips?

Happy Memorial day