When I see "interface buffer" or "packet buffer" listed on a vendor spec sheet, what exactly is this?
I know it's basically memory space that holds packets waiting to be transferred, right?
So when you're configurating scheduling and queuing you're basically affecting how many of which packets can enter the buffer, and which order they leave the buffer?
Is the buffer shared amongst all ports? Is it different from the switch memory which is usually listed as a different spec?
Why is it so different among vendors, or difficult to have big buffers? I was comparing two different vendors and one had a 30 meg packet buffer, the other boasted a 60 meg buffer... even though CPU, memory, asic were all identical. (Arista "Deep Buffers")
Is it true? Is it marketing buzzword?
Also on some switches I'm told you can adjust the buffer size. How is that possible if it's hardware.
As you can see my curious mind has so many questions. Please enlighten me, great sages!
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